soc/amd/picasso: snapshot chipset state early in boot sequence

Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 2 insertions, 4 deletions

diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index ff8e4360efcf..df2d0d0f4155 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -314,11 +314,9 @@ void southbridge_init(void *chip_info)
 	i2c_soc_init();
 	sb_init_acpi_ports();
 
-	state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
-	if (state) {
-		acpi_fill_pm_gpe_state(state);
+	state = cbmem_find(CBMEM_ID_POWER_STATE);
+	if (state)
 		acpi_pm_gpe_add_events_print_events(state);
-	}
 	acpi_clear_pm_gpe_status();
 
 	al2ahb_clock_gate();