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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-30 18:18:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-02 21:27:03 +0000 |
| commit | 6443ad4a53ab65a2a9c1d29f422644e450c04cd7 (patch) | |
| tree | 4843082fa04ab74fd08b53aa01eb65165e8edb4f /src/soc/amd/picasso/uart.c | |
| parent | 5b3831c75abe5fc50739984eaa70fbada2575bb7 (diff) | |
| download | coreboot-6443ad4a53ab65a2a9c1d29f422644e450c04cd7.tar.gz coreboot-6443ad4a53ab65a2a9c1d29f422644e450c04cd7.tar.bz2 coreboot-6443ad4a53ab65a2a9c1d29f422644e450c04cd7.zip | |
soc/amd: factor out common AOAC device enable and status query functions
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/uart.c')
| -rw-r--r-- | src/soc/amd/picasso/uart.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 1aa42ef47b51..a71a0e97d9a1 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -6,6 +6,7 @@ #include <device/mmio.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <soc/southbridge.h> #include <soc/gpio.h> #include <soc/uart.h> |