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| author | Terry Chen <terry_chen@wistron.corp-partner.google.com> | 2022-02-22 16:50:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 01:25:32 +0000 |
| commit | 95f8f92451097ad52ab49affbe21ea5782e6146d (patch) | |
| tree | 628529b908e34ed80b08050b2bcf4a87c922884b /src/soc/amd/picasso | |
| parent | 4cee77bce3d7a7426ccc24b2d7d92f4d87955f38 (diff) | |
| download | coreboot-95f8f92451097ad52ab49affbe21ea5782e6146d.tar.gz coreboot-95f8f92451097ad52ab49affbe21ea5782e6146d.tar.bz2 coreboot-95f8f92451097ad52ab49affbe21ea5782e6146d.zip | |
mb/google/brya: Add SPD configs for Crota
Add a mem_parts_used.txt for Crota, containing the
memory parts used in proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
H9JCNNNCP3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:215443524
TEST=emerge-brya coreboot
Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/amd/picasso')
0 files changed, 0 insertions, 0 deletions