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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-09 00:16:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-09 23:20:55 +0000 |
| commit | b455dd3486a7b2e0b8d98c907cb9389c8283faff (patch) | |
| tree | 5aab030df934195c12962afcd25520a2fa935a8e /src/soc/amd/picasso | |
| parent | 90d79a751b1c85f436ceb77f39cbeab4c8068b36 (diff) | |
| download | coreboot-b455dd3486a7b2e0b8d98c907cb9389c8283faff.tar.gz coreboot-b455dd3486a7b2e0b8d98c907cb9389c8283faff.tar.bz2 coreboot-b455dd3486a7b2e0b8d98c907cb9389c8283faff.zip | |
soc/amd/cezanne,picasso/include/southbridge: fix typo in define
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16
of the misc I2C pad control registers is defined as BiasCrtEn, so rename
I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index f547f860a823..300f458fa78e 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -115,7 +115,7 @@ #define I2C_PAD_CTRL_CAP_UP BIT(13) #define I2C_PAD_CTRL_RES_DOWN BIT(14) #define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) |