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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-11 17:05:11 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 22:14:05 +0000 |
| commit | 2f478b85caac41b1ba2ade33380b4273474c46a0 (patch) | |
| tree | 8e6c4dc68ef96f7826c3759057ccce04b4d80c06 /src/soc/amd/sabrina/include | |
| parent | cea684df9fb1c9fc5164d8a26986fb5215deead7 (diff) | |
| download | coreboot-2f478b85caac41b1ba2ade33380b4273474c46a0.tar.gz coreboot-2f478b85caac41b1ba2ade33380b4273474c46a0.tar.bz2 coreboot-2f478b85caac41b1ba2ade33380b4273474c46a0.zip | |
soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs
Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/include')
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h b/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h index 5d2853335575..a3f8b82ddc63 100644 --- a/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h @@ -59,7 +59,8 @@ #define PIRQ_UART0 0x74 /* UART0 */ #define PIRQ_UART1 0x75 /* UART1 */ #define PIRQ_I2C4 0x76 /* I2C4 */ -#define PIRQ_I2C5 0x77 /* I2C5 */ -/* 0x78-0x7f reserved */ +#define PIRQ_UART4 0x77 /* UART4 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ #endif /* AMD_SABRINA_AMD_PCI_INT_DEFS_H */ |