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| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-07-14 11:06:30 -0400 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-16 22:52:21 +0000 |
| commit | 475e2824a8d08e6117632e1f67910f8266f1872e (patch) | |
| tree | 94d519875235bf910b472432924e06504bcf77a8 /src/soc/amd/sabrina | |
| parent | 8de0e369e34a08c559a7a6e900e2584a9d1a9ff1 (diff) | |
| download | coreboot-475e2824a8d08e6117632e1f67910f8266f1872e.tar.gz coreboot-475e2824a8d08e6117632e1f67910f8266f1872e.tar.bz2 coreboot-475e2824a8d08e6117632e1f67910f8266f1872e.zip | |
soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config option
The APOB in sabrina is larger than in cezanne/picasso and no longer
fits in the previously allocated 64K space for it. Other symbols are
placed immediately after the APOB region and end up corrupting the APOB
data on sabrina.
Add a Kconfig option to specify the APOB size in DRAM to reserve enough
memory and increase the size for sabrina to 128K
TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN.
Build chausie and verify symbols do not overlap _apob region
BUG=b:224056176
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/sabrina')
| -rw-r--r-- | src/soc/amd/sabrina/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/root_complex.c | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 654c6e393530..48d61be03855 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -123,9 +123,13 @@ config PSP_APOB_DRAM_ADDRESS Location in DRAM where the PSP will copy the AGESA PSP Output Block. +config PSP_APOB_DRAM_SIZE + hex + default 0x20000 + config PSP_SHAREDMEM_BASE hex - default 0x2011000 if VBOOT + default 0x2021000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index 76ed7650e852..c911106e6b3a 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -88,7 +88,7 @@ struct dptc_input { * | PSP shared (vboot workbuf) | * | (PSP_SHAREDMEM_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | + * | APOB (128KiB) | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS * | Early BSP stack | * | (EARLYRAM_BSP_STACK_SIZE) | |