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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-04-20 14:08:09 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-22 21:11:58 +0000 |
| commit | b94d3681e1c0f96f026ce0e2fbc64759f070b580 (patch) | |
| tree | 4bb2820b457dc3232aa99796472366a9a5488c63 /src/soc/amd/sabrina | |
| parent | 9077d65b5b723c13e6d891e3476712ee18d7364e (diff) | |
| download | coreboot-b94d3681e1c0f96f026ce0e2fbc64759f070b580.tar.gz coreboot-b94d3681e1c0f96f026ce0e2fbc64759f070b580.tar.bz2 coreboot-b94d3681e1c0f96f026ce0e2fbc64759f070b580.zip | |
soc/amd/sabrina: enable warm reset functionality
Commit 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (soc/amd/cezanne: Force
resets to be cold) forced all resets on Cezanne to be cold resets to
work around a bug. Since the bug is fixed on Sabrina, this workaround
copied over from the Cezanne code isn't needed here, so sort-of revert
what the patch referenced above changed for Cezanne in the Sabrina code.
BUG=b:229105416
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785e43124a9a969eeb129454e6e15dc245625250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/sabrina')
| -rw-r--r-- | src/soc/amd/sabrina/fch.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/reset.c | 4 |
2 files changed, 1 insertions, 9 deletions
diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c index 9be7dd891234..a768989b64f2 100644 --- a/src/soc/amd/sabrina/fch.c +++ b/src/soc/amd/sabrina/fch.c @@ -127,11 +127,6 @@ static void fch_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -198,7 +193,6 @@ static void cgpll_clock_gate_init(void) void fch_init(void *chip_info) { - fch_init_resets(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/sabrina/reset.c b/src/soc/amd/sabrina/reset.c index 90fedda9047e..28e60b630738 100644 --- a/src/soc/amd/sabrina/reset.c +++ b/src/soc/amd/sabrina/reset.c @@ -19,9 +19,7 @@ void do_cold_reset(void) void do_warm_reset(void) { - /* Warm resets are not supported and must be executed as cold */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); + /* Assert reset signals only. */ outb(RST_CPU | SYS_RST, RST_CNT); } |