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| author | Martin Roth <martinroth@chromium.org> | 2018-05-02 15:15:45 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-04 01:04:15 +0000 |
| commit | 4821789e7cfb090fcc0bf9814852ffa7258ac96d (patch) | |
| tree | 8c2087f3c61603b891abc6c56f6f22c32323be8c /src/soc/amd/stoneyridge/BiosCallOuts.c | |
| parent | 59114579a24c3371b98f3205fd668e3a0257ab34 (diff) | |
| download | coreboot-4821789e7cfb090fcc0bf9814852ffa7258ac96d.tar.gz coreboot-4821789e7cfb090fcc0bf9814852ffa7258ac96d.tar.bz2 coreboot-4821789e7cfb090fcc0bf9814852ffa7258ac96d.zip | |
soc/amd/stoneyridge: Remove USB30PortInit setting
This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/BiosCallOuts.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/BiosCallOuts.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c6eef1a32fdd..d2f7a326181c 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -68,9 +68,6 @@ AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams_env->Usb.Xhci0Enable = FALSE; FchParams_env->Usb.Xhci1Enable = FALSE; - /* 8: If USB3 port is unremoveable. */ - FchParams_env->Usb.USB30PortInit = 8; - /* SATA configuration */ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { |