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| author | Justin TerAvest <teravest@chromium.org> | 2018-01-24 14:23:12 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-25 22:35:38 +0000 |
| commit | 13101a7be09d9db8a8e3a784a262a6d122ff3503 (patch) | |
| tree | 507d76cb01d00bc836208127cf8209709a67922a /src/soc/amd/stoneyridge/chip.h | |
| parent | 949d666b5cffcdb16c3aaa06092e1b38ae27955c (diff) | |
| download | coreboot-13101a7be09d9db8a8e3a784a262a6d122ff3503.tar.gz coreboot-13101a7be09d9db8a8e3a784a262a6d122ff3503.tar.bz2 coreboot-13101a7be09d9db8a8e3a784a262a6d122ff3503.zip | |
soc/amd/stoneyridge: Add I2C devicetree support.
This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.
BUG=b:72121803
Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 5688a7397deb..c98734d5f328 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -19,11 +19,16 @@ #include <stddef.h> #include <stdint.h> #include <commonlib/helpers.h> +#include <drivers/i2c/designware/dw_i2c.h> +#include <soc/gpio.h> +#include <arch/acpi_device.h> #define MAX_NODES 1 #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 +#define STONEY_I2C_DEV_MAX 4 + struct soc_amd_stoneyridge_config { u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; enum { @@ -44,6 +49,8 @@ struct soc_amd_stoneyridge_config { /* Used if UMAMODE_SPECIFIED_SIZE is set. */ size_t uma_size; + + struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX]; }; typedef struct soc_amd_stoneyridge_config config_t; |