soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1

Despite Stoneyridge being one only SoC in soc/amd that uses the first
generation of the PSP mailblox interface, this code is common for all
SoCs that use the first PSP mailbox interface generation, so move it to
the common PSP generation 1 code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 29 deletions

diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index b001d5f755ef..e2a74bd611ad 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -3,8 +3,6 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/northbridge.h>
 #include <soc/southbridge.h>
@@ -30,30 +28,3 @@ void soc_enable_psp_early(void)
 	cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 	pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
 };
-
-void *soc_get_mbox_address(void)
-{
-	uintptr_t psp_mmio;
-
-	/* Check for presence of the PSP */
-	if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
-		printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n",
-			PSP_DEV, PSP_FUNC);
-		return 0;
-	}
-
-	/* Determine if Bar3Hide has been set, and if hidden get the base from
-	 * the MSR instead. */
-	if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
-		psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
-		if (!psp_mmio) {
-			printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n");
-			return 0;
-		}
-	} else {
-		psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) &
-				~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	}
-
-	return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
-}