summaryrefslogtreecommitdiffstats
path: root/src/soc/amd/stoneyridge/southbridge.c
diff options
context:
space:
mode:
authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-05-03 13:06:55 -0600
committerMartin Roth <martinroth@google.com>2019-06-06 19:20:38 +0000
commit19cae7c8915d6fa482cc0a8997dd89e5e11a2509 (patch)
tree8f8bede07069218a4a234c807f65c132f906be11 /src/soc/amd/stoneyridge/southbridge.c
parentaf159d4416b87adf9c741846bf4feeafa0789f2a (diff)
downloadcoreboot-19cae7c8915d6fa482cc0a8997dd89e5e11a2509.tar.gz
coreboot-19cae7c8915d6fa482cc0a8997dd89e5e11a2509.tar.bz2
coreboot-19cae7c8915d6fa482cc0a8997dd89e5e11a2509.zip
soc/amd/stoneyridge: Remove sb_util.c
Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk(). Relocate the remaining functions to get/save UMA information to southbridge.c. Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 10a23f2737fd..45408ead02c8 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -649,3 +649,27 @@ static void set_pci_irqs(void *unused)
* on entry into BS_DEV_ENABLE.
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
+
+void save_uma_size(uint32_t size)
+{
+ biosram_write32(BIOSRAM_UMA_SIZE, size);
+}
+
+void save_uma_base(uint64_t base)
+{
+ biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
+ biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
+}
+
+uint32_t get_uma_size(void)
+{
+ return biosram_read32(BIOSRAM_UMA_SIZE);
+}
+
+uint64_t get_uma_base(void)
+{
+ uint64_t base;
+ base = biosram_read32(BIOSRAM_UMA_BASE);
+ base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
+ return base;
+}