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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-06-16 18:46:00 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-17 18:44:04 +0000 |
| commit | dac1f66c6c889962e355277570f9c36b747eec8a (patch) | |
| tree | 3b2550c102cf9effb5000a4c12cedcb98157dcc7 /src/soc/amd/stoneyridge/southbridge.c | |
| parent | 8bca2b18bcb32d07a1be52dea0cee17567e4baec (diff) | |
| download | coreboot-dac1f66c6c889962e355277570f9c36b747eec8a.tar.gz coreboot-dac1f66c6c889962e355277570f9c36b747eec8a.tar.bz2 coreboot-dac1f66c6c889962e355277570f9c36b747eec8a.zip | |
soc/amd/stoneyridge: factor out AOAC offset defines
Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b7d7b5e48651..d9dd78fe13a8 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -27,6 +27,7 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/acpi.h> +#include <soc/aoac_defs.h> #include <soc/lpc.h> #include <soc/nvs.h> #include <types.h> |