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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-05-24 20:25:58 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-06-22 12:30:15 +0000 |
| commit | 27d6299d51744bda549b7764b8fde909ad812e33 (patch) | |
| tree | c30a57ff78e57c9c79a74c4b27cc6e5dfbc94a49 /src/soc/amd/stoneyridge | |
| parent | 37b161fb96c602765fef9f64415f809830b915a4 (diff) | |
| download | coreboot-27d6299d51744bda549b7764b8fde909ad812e33.tar.gz coreboot-27d6299d51744bda549b7764b8fde909ad812e33.tar.bz2 coreboot-27d6299d51744bda549b7764b8fde909ad812e33.zip | |
device/resource: Add _kb postfix for resource allocators
There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 2166ef477fb1..a47ef25e728b 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -396,23 +396,23 @@ void domain_read_resources(struct device *dev) pci_domain_read_resources(dev); /* 0x0 -> 0x9ffff */ - ram_resource(dev, idx++, 0, 0xa0000 / KiB); + ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 -> 0xbffff: legacy VGA */ - mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); /* 0xc0000 -> 0xfffff: Option ROM */ - reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); /* * 0x100000 (1MiB) -> low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_resource(dev, idx++, (1 * MiB) / KiB, + ram_resource_kb(dev, idx++, (1 * MiB) / KiB, (mem_useable - (1 * MiB)) / KiB); /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ - reserved_ram_resource(dev, idx++, mem_useable / KiB, + reserved_ram_resource_kb(dev, idx++, mem_useable / KiB, (tom.lo - mem_useable) / KiB); /* If there is memory above 4GiB */ @@ -424,12 +424,12 @@ void domain_read_resources(struct device *dev) high_mem_useable = ((uint64_t)high_tom.lo | ((uint64_t)high_tom.hi << 32)); - ram_resource(dev, idx++, (4ull * GiB) / KiB, + ram_resource_kb(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB)); /* High top usable RAM -> high top RAM */ if (uma_base >= (4ull * GiB)) { - reserved_ram_resource(dev, idx++, uma_base / KiB, + reserved_ram_resource_kb(dev, idx++, uma_base / KiB, uma_size / KiB); } } |