soc/amd/stoneyridge: use common fch_spi_early_init

All SPI interface setup related functionality that Stoneyridge
implemented in its southbridge code is already present in the common AMD
SoC code, so use that code instead.

The common fch_spi_early_init function requires the SPI controller's
base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right
before it. fch_spi_early_init then calls lpc_enable_spi_rom and
lpc_enable_spi_prefetch which can be removed from the board code now.
Next it calls fch_spi_configure_4dw_burst which does the same as the now
removed sb_disable_4dw_burst function when
SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default.
This option can also only be set to y for SoCs that aren't Stoneyridge.
Finally fch_spi_early_init calls fch_spi_config_modes which configures
the SPI mode and speed settings according to the Kconfig settings and
the settings in the amdfw part. On Kahlee this was done by calls to
sb_read_mode and sb_set_spi100 before. The previous patch added the
remaining Kconfig settings, so the resulting register values don't
change in the non-EM100 case. In the EM100 case the TPM speed is changed
from 64 to 16 MHz.

TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode
with a first-generation EM100 results in Google/Barla reaching the
payload and the show_spi_speeds_and_modes call in bootblock prints the
expected settings:

relevant bootblock console output in non-EM100 case:

SPI normal read speed: 33.33 MHz
SPI fast read speed: 66.66 Mhz
SPI alt read speed: 66.66 Mhz
SPI TPM read speed: 66.66 Mhz
SPI100: Enabled
SPI Read Mode: Dual IO (1-2-2)

relevant bootblock console output in EM100 case:

SPI normal read speed: 16.66 MHz
SPI fast read speed: 16.66 MHz
SPI alt read speed: 16.66 MHz
SPI TPM read speed: 16.66 MHz
SPI100: Enabled
SPI Read Mode: Normal Read (up to 33M)

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

2 files changed, 3 insertions, 69 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 74e949809d4b..27737514ce88 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -142,41 +142,6 @@
 #define SATA_CAPABILITIES_REG		0xfc
 #define SATA_CAPABILITY_SPM		BIT(12)
 
-#define SPI_CNTRL0			0x00
-#define   SPI_BUSY			BIT(31)
-#define   SPI_READ_MODE_MASK		(BIT(30) | BIT(29) | BIT(18))
-/* Nominal is 16.7MHz on older devices, 33MHz on newer */
-#define   SPI_READ_MODE_NOM		0x00000000
-#define   SPI_READ_MODE_DUAL112		(          BIT(29)          )
-#define   SPI_READ_MODE_QUAD114		(          BIT(29) | BIT(18))
-#define   SPI_READ_MODE_DUAL122		(BIT(30)                    )
-#define   SPI_READ_MODE_QUAD144		(BIT(30) |           BIT(18))
-#define   SPI_READ_MODE_NORMAL66	(BIT(30) | BIT(29)          )
-#define   SPI_READ_MODE_FAST		(BIT(30) | BIT(29) | BIT(18))
-#define   SPI_ACCESS_MAC_ROM_EN		BIT(22)
-#define   SPI_FIFO_PTR_CLR		BIT(20)
-#define   SPI_ARB_ENABLE		BIT(19)
-#define   EXEC_OPCODE			BIT(16)
-
-#define SPI100_ENABLE			0x20
-#define   SPI_USE_SPI100		BIT(0)
-
-/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
-#define SPI100_SPEED_CONFIG		0x22
-#define   SPI_SPEED_66M			(0x0)
-#define   SPI_SPEED_33M			(                  BIT(0))
-#define   SPI_SPEED_22M			(         BIT(1)         )
-#define   SPI_SPEED_16M			(         BIT(1) | BIT(0))
-#define   SPI_SPEED_100M		(BIT(2)                  )
-#define   SPI_SPEED_800K		(BIT(2) |          BIT(0))
-#define   SPI_NORM_SPEED_NEW_SH		12
-#define   SPI_FAST_SPEED_NEW_SH		8
-#define   SPI_ALT_SPEED_NEW_SH		4
-#define   SPI_TPM_SPEED_NEW_SH		0
-
-#define SPI100_HOST_PREF_CONFIG		0x2c
-#define   SPI_RD4DW_EN_HOST		BIT(15)
-
 /* Platform Security Processor D8F0 */
 void soc_enable_psp_early(void);
 
@@ -219,8 +184,6 @@ void fch_final(void *chip_info);
 
 void enable_aoac_devices(void);
 void fch_clk_output_48Mhz(u32 osc);
-void sb_read_mode(u32 mode);
-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 
 /*
  * Call the mainboard to get the USB Over Current Map. The mainboard
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 3b2cba6352c0..2ffbc92e0124 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -227,35 +227,6 @@ void fch_clk_output_48Mhz(u32 osc)
 	misc_write32(MISC_CLK_CNTL1, ctrl);
 }
 
-static void sb_init_spi_base(void)
-{
-	/* Make sure the base address is predictable */
-	lpc_set_spibase(SPI_BASE_ADDRESS);
-	lpc_enable_spi_rom(SPI_ROM_ENABLE);
-}
-
-void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
-{
-	spi_write16(SPI100_SPEED_CONFIG,
-				(norm << SPI_NORM_SPEED_NEW_SH) |
-				(fast << SPI_FAST_SPEED_NEW_SH) |
-				(alt << SPI_ALT_SPEED_NEW_SH) |
-				(tpm << SPI_TPM_SPEED_NEW_SH));
-	spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE));
-}
-
-static void sb_disable_4dw_burst(void)
-{
-	spi_write16(SPI100_HOST_PREF_CONFIG,
-			spi_read16(SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST);
-}
-
-void sb_read_mode(u32 mode)
-{
-	spi_write32(SPI_CNTRL0,
-			(spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode);
-}
-
 static void setup_spread_spectrum(int *reboot)
 {
 	uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
@@ -334,9 +305,9 @@ void bootblock_fch_early_init(void)
 	sb_enable_lpc();
 	lpc_enable_port80();
 	sb_lpc_decode();
-	lpc_enable_spi_prefetch();
-	sb_init_spi_base();
-	sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
+	/* Make sure the base address is predictable */
+	lpc_set_spibase(SPI_BASE_ADDRESS);
+	fch_spi_early_init();
 	fch_smbus_init();
 	fch_enable_cf9_io();
 	setup_spread_spectrum(&reboot);