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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 02:44:41 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-08 15:52:41 +0000 |
| commit | 505ccc8b516cd880d6761eac5a35d576eff1de2f (patch) | |
| tree | 20c72d69be9876ac3834303574d9d61aeadb8cbd /src/soc/amd/stoneyridge | |
| parent | 94246660f19059eee418e0b8257c7b13888757d1 (diff) | |
| download | coreboot-505ccc8b516cd880d6761eac5a35d576eff1de2f.tar.gz coreboot-505ccc8b516cd880d6761eac5a35d576eff1de2f.tar.bz2 coreboot-505ccc8b516cd880d6761eac5a35d576eff1de2f.zip | |
soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scope
The PCI root complex itself isn't on an enumerable bus, so without
providing an _STA method, the device will still be assumed to be present
and visible, so this won't change behavior. This also brings Stoneyridge
more in line with the newer SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I663c7bcba89ffe25d0819d83461cb95e10f49028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75671
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/northbridge.asl | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index af62abdbf268..6bf229329d77 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -11,11 +11,6 @@ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ Return(0) } -Method(_STA, 0, NotSerialized) -{ - Return(0x0F) /* Status is visible */ -} - Method(_PRT,0, NotSerialized) { If(PICM) |