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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-02-15 10:59:41 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-16 07:05:14 +0000 |
| commit | 796147f5ca772608e4f8acd6f794c73806e63d30 (patch) | |
| tree | bb9a99c8e26b2c00526471f816b204262ea9576d /src/soc/amd/stoneyridge | |
| parent | 46b409da483ebfc8d9c868c713f5ad68b62c808e (diff) | |
| download | coreboot-796147f5ca772608e4f8acd6f794c73806e63d30.tar.gz coreboot-796147f5ca772608e4f8acd6f794c73806e63d30.tar.bz2 coreboot-796147f5ca772608e4f8acd6f794c73806e63d30.zip | |
soc/amd/stoneyridge: Use common prepare_and_run_postcar
This reduces boilerplate postcar frame setup.
Change-Id: I8e258113c90ee49864ceddf36ea296ba6f83afe4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 28 |
1 files changed, 8 insertions, 20 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index a2037fced688..aa54aee26678 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -23,6 +23,7 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> +#include <stdint.h> #include "chip.h" @@ -50,7 +51,6 @@ static void bsp_agesa_call(void) asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; - uintptr_t top_of_ram; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -121,28 +121,16 @@ asmlinkage void car_stage_entry(void) smm_list_regions(); post_code(0x44); - if (postcar_frame_init(&pcf)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + prepare_and_run_postcar(&pcf); +} - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); /* Cache the TSEG region */ - postcar_enable_tseg_cache(&pcf); - - post_code(0x45); - run_postcar_phase(&pcf); - - post_code(0x50); /* Should never see this post code. */ + postcar_enable_tseg_cache(pcf); } void SetMemParams(AMD_POST_PARAMS *PostParams) |