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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-05 12:11:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-18 20:52:26 +0000 |
| commit | 885efa1102fd39bb7d0558d6d0ad9d10284e1a72 (patch) | |
| tree | a0a6a32dfbced9a15a093aef8b15b2bb0d6154a2 /src/soc/amd/stoneyridge | |
| parent | dd9481542f0b989355fefaa1226c890dd60e6889 (diff) | |
| download | coreboot-885efa1102fd39bb7d0558d6d0ad9d10284e1a72.tar.gz coreboot-885efa1102fd39bb7d0558d6d0ad9d10284e1a72.tar.bz2 coreboot-885efa1102fd39bb7d0558d6d0ad9d10284e1a72.zip | |
soc/amd/stoneyridge: Use newer function for resource declarations
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I2d01424731b149daa3d3378d66855ee5e074473b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76290
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b4c18d3587e7..ecdbe4fee91d 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -363,24 +363,22 @@ void domain_read_resources(struct device *dev) fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); /* 0x0 -> 0x9ffff */ - ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); + ram_range(dev, idx++, 0, 0xa0000); /* 0xa0000 -> 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); + mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); /* 0xc0000 -> 0xfffff: Option ROM */ - reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); /* * 0x100000 (1MiB) -> low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_resource_kb(dev, idx++, (1 * MiB) / KiB, - (mem_useable - (1 * MiB)) / KiB); + ram_from_to(dev, idx++, 1 * MiB, mem_useable); /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ - reserved_ram_resource_kb(dev, idx++, mem_useable / KiB, - (tom - mem_useable) / KiB); + reserved_ram_from_to(dev, idx++, mem_useable, tom); /* If there is memory above 4GiB */ if (high_tom >> 32) { @@ -390,13 +388,11 @@ void domain_read_resources(struct device *dev) else high_mem_useable = high_tom; - ram_resource_kb(dev, idx++, (4ull * GiB) / KiB, - ((high_mem_useable - (4ull * GiB)) / KiB)); + ram_from_to(dev, idx++, 4ull * GiB, high_mem_useable); /* High top usable RAM -> high top RAM */ if (uma_base >= (4ull * GiB)) { - reserved_ram_resource_kb(dev, idx++, uma_base / KiB, - uma_size / KiB); + reserved_ram_range(dev, idx++, uma_base, uma_size); } } } |