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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-03-02 23:36:55 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-03 22:45:41 +0000 |
| commit | af17f0b7ce06f98586d31d1a2a50fb4fbc9cffd7 (patch) | |
| tree | 880a111c7846288ecde83be3b9fea65d3cb4705a /src/soc/amd/stoneyridge | |
| parent | b1197af7f5aa18b17160f0c5fba9869482891cd2 (diff) | |
| download | coreboot-af17f0b7ce06f98586d31d1a2a50fb4fbc9cffd7.tar.gz coreboot-af17f0b7ce06f98586d31d1a2a50fb4fbc9cffd7.tar.bz2 coreboot-af17f0b7ce06f98586d31d1a2a50fb4fbc9cffd7.zip | |
soc/amd/*/northbridge,root_complex: add comment about PCI BARs
Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 0384e00b88bb..85ef19ef4d65 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -60,6 +60,9 @@ static void read_resources(struct device *dev) unsigned int idx = 0; struct resource *res; + /* The northbridge has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in |