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| author | Martin Roth <martinroth@chromium.org> | 2021-08-11 13:27:45 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-30 18:54:16 +0000 |
| commit | fd078d85d01810a4f03a8c21d454c04d9e2d3ae4 (patch) | |
| tree | 7689d939d1ee14f24ccbcd2be1701bdeaeb0cbe4 /src/soc/amd/stoneyridge | |
| parent | e582e710b8ed6315a2a62b8c6d745af218d434cb (diff) | |
| download | coreboot-fd078d85d01810a4f03a8c21d454c04d9e2d3ae4.tar.gz coreboot-fd078d85d01810a4f03a8c21d454c04d9e2d3ae4.tar.bz2 coreboot-fd078d85d01810a4f03a8c21d454c04d9e2d3ae4.zip | |
soc/amd: Show SPI settings in bootblock
BUG=b:194919326
TEST=See SPI settings in bootblock
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 5f5fc72bfcb1..7493770fac98 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -357,6 +357,7 @@ void bootblock_fch_init(void) { pm_set_power_failure_state(); fch_print_pmxc0_status(); + show_spi_speeds_and_modes(); } static void fch_init_acpi_ports(void) |