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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 20:43:09 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-31 22:55:53 +0000 |
| commit | 1786601b524f380ebd72bc63083e7e97a8996198 (patch) | |
| tree | 8011a5acd782dc0aeedb7ed8383a0848b4fd5019 /src/soc/amd | |
| parent | 26d54b70e2821ea383862cc7795b669dde80ca43 (diff) | |
| download | coreboot-1786601b524f380ebd72bc63083e7e97a8996198.tar.gz coreboot-1786601b524f380ebd72bc63083e7e97a8996198.tar.bz2 coreboot-1786601b524f380ebd72bc63083e7e97a8996198.zip | |
soc/amd/common/block/cpu/tsc/Makefile: order targets by stage
Now that only one build target per stage is included in the build
depending on CONFIG_SOC_AMD_COMMON_BLOCK_TSC being set, don't use a
separate ifeq block for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74017
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/cpu/tsc/Makefile.inc | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index ade49707ca5a..65e849a36ee3 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -3,33 +3,24 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC),y) - -bootblock-y += tsc_freq.c - -verstage_x86-y += tsc_freq.c - -romstage-y += tsc_freq.c - -ramstage-y += tsc_freq.c - -smm-y += tsc_freq.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c |