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| author | Jeff Daly <jeffd@silicom-usa.com> | 2022-01-11 15:44:20 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-17 14:53:18 +0000 |
| commit | 5b67ad0a5f7a1ba9d5a4dc46c7d2dec1665f00d7 (patch) | |
| tree | 39ab6e8ba32cf289083ae6df52ed8d303adb7392 /src/soc/amd | |
| parent | e5ac30060298626cf12972209ea81a77d0569cde (diff) | |
| download | coreboot-5b67ad0a5f7a1ba9d5a4dc46c7d2dec1665f00d7.tar.gz coreboot-5b67ad0a5f7a1ba9d5a4dc46c7d2dec1665f00d7.tar.bz2 coreboot-5b67ad0a5f7a1ba9d5a4dc46c7d2dec1665f00d7.zip | |
soc/intel/denverton_ns: enable Denverton to use common msr defines
Use Intel common SoC msr.h for Denverton refactor
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions