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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-23 16:32:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 17:44:11 +0000 |
| commit | 972d9f2cce2792b847c4c1879f5b52c19585c37c (patch) | |
| tree | 87166acd957448e6b262a331106e7a276806043c /src/soc/amd | |
| parent | 887d4ed912ef80afbf7827150f52e207edc9c033 (diff) | |
| download | coreboot-972d9f2cce2792b847c4c1879f5b52c19585c37c.tar.gz coreboot-972d9f2cce2792b847c4c1879f5b52c19585c37c.tar.bz2 coreboot-972d9f2cce2792b847c4c1879f5b52c19585c37c.zip | |
arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/iomap.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 5 |
4 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index a6efce72b53e..fc04b256a8c9 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -15,11 +15,6 @@ #define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 -#include <arch/hpet.h> /* This will be removed in a follow-up patch */ -#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS -#error HPET address must be 0xfed00000 -#endif - /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1ce581ec3ff1..853008bcbc59 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -10,11 +10,6 @@ #define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 -#include <arch/hpet.h> /* This will be removed in a follow-up patch */ -#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS -#error HPET address must be 0xfed00000 -#endif - /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 #define AL2AHB_CONTROL_CLK_OFFSET 0x10 diff --git a/src/soc/amd/sabrina/include/soc/iomap.h b/src/soc/amd/sabrina/include/soc/iomap.h index cfe418488867..7f9746b97fc7 100644 --- a/src/soc/amd/sabrina/include/soc/iomap.h +++ b/src/soc/amd/sabrina/include/soc/iomap.h @@ -15,11 +15,6 @@ #define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 -#include <arch/hpet.h> /* This will be removed in a follow-up patch */ -#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS -#error HPET address must be 0xfed00000 -#endif - /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 75c09734d8f3..76e6e778e2dc 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -16,11 +16,6 @@ #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 -#include <arch/hpet.h> /* This will be removed in a follow-up patch */ -#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS -#error HPET address must be 0xfed00000 -#endif - #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 |