diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-04-02 13:47:09 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-04-05 16:39:11 +0000 |
| commit | b95f848766be07f35f32a80be10e8b472072d514 (patch) | |
| tree | ce9ecee1541c16c3faf66015350f1e3b6050a4f7 /src/soc/amd | |
| parent | 61ac1bc53022f3baa0e5a753bd75d639cb95718a (diff) | |
| download | coreboot-b95f848766be07f35f32a80be10e8b472072d514.tar.gz coreboot-b95f848766be07f35f32a80be10e8b472072d514.tar.bz2 coreboot-b95f848766be07f35f32a80be10e8b472072d514.zip | |
soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/espi.h | 7 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 3 |
3 files changed, 3 insertions, 11 deletions
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 0e351a9ce262..5dca21176468 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -67,8 +67,6 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - espi_clear_decodes(); + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) espi_setup(); - } } diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index f5e7d31851b9..435b81f7e0f9 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -101,13 +101,6 @@ int espi_open_io_window(uint16_t base, size_t size); int espi_open_mmio_window(uint32_t base, size_t size); /* - * Clear all configured eSPI memory and I/O decode ranges. This is useful for changing - * the decodes, or if something else has previously setup decode windows that conflict - * with the windows that coreboot needs. - */ -void espi_clear_decodes(void); - -/* * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading * SPIBASE. This is required for cases where verstage runs on PSP. */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 0b690b821b25..f120082542fe 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -98,7 +98,7 @@ static int espi_get_unused_io_window(void) return -1; } -void espi_clear_decodes(void) +static void espi_clear_decodes(void) { unsigned int idx; @@ -894,6 +894,7 @@ int espi_setup(void) espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI); espi_write32(ESPI_SLAVE0_INT_EN, 0); espi_clear_status(); + espi_clear_decodes(); /* * Boot sequence: Step 1 |