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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-10-25 18:18:36 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-26 17:44:47 +0000 |
| commit | bf26485d36600384b10f0a2f934ab2cda47de114 (patch) | |
| tree | 908bd610c7cf69608305021e72ff4c7c64924251 /src/soc/amd | |
| parent | 886c1ffc652efe7e0d3345dfb34a38669041e467 (diff) | |
| download | coreboot-bf26485d36600384b10f0a2f934ab2cda47de114.tar.gz coreboot-bf26485d36600384b10f0a2f934ab2cda47de114.tar.bz2 coreboot-bf26485d36600384b10f0a2f934ab2cda47de114.zip | |
soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES
Instead of using magic constants for the fch_pic_routing and
fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the
common code headers and use this definition. This also allows to drop
the static assert for the array sizes. In the Stoneyridge mainboard code
the equivalent arrays are named mainboard_picr_data and
mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array
size there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/amd_pci_util.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 654385343941..c766d501bd42 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -11,6 +11,8 @@ #define PCI_INTR_INDEX 0xc00 #define PCI_INTR_DATA 0xc01 +#define FCH_IRQ_ROUTING_ENTRIES 0x80 + struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; |