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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2014-12-12 13:53:22 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-13 12:19:38 +0200 |
| commit | b9d961550ce07951b472ae558281e288413ab445 (patch) | |
| tree | a216653e0b12621d998a8cafa77f2481d5173a1c /src/soc/imgtec | |
| parent | 9b99d7b435f24a2e3a70c6b29a4dba13efc3ef47 (diff) | |
| download | coreboot-b9d961550ce07951b472ae558281e288413ab445.tar.gz coreboot-b9d961550ce07951b472ae558281e288413ab445.tar.bz2 coreboot-b9d961550ce07951b472ae558281e288413ab445.zip | |
urara: add support for DMA coherent memory area
The information about the DMA memory area is further passed
through the coreboot table to the payload.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA; DMA memory area was used to test the
functionality of the DWC2 USB controller driver; behavior was
as expected.
BRANCH=none
Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a
Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/235910
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9593
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/imgtec')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 1c7ea9a74c9b..c3c6c07ebf45 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -36,4 +36,6 @@ SECTIONS /* Let's use SRAM for CBFS cache. */ CBFS_CACHE(0x9b000000, 64K) + /* DMA coherent area: end of available DRAM, uncached */ + DMA_COHERENT(0xAFF00000, 1M) } |