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| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-10-30 20:43:50 -0700 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-11-02 13:31:33 +0000 |
| commit | 8bde652241ecb8356540b3a418012d3c7e570ac3 (patch) | |
| tree | 4dfd2469fca03e5e9f97f82f766245d4bec33180 /src/soc/intel/alderlake/Kconfig | |
| parent | eb93808fa53d95900ea42b42f8c943c282d99973 (diff) | |
| download | coreboot-8bde652241ecb8356540b3a418012d3c7e570ac3.tar.gz coreboot-8bde652241ecb8356540b3a418012d3c7e570ac3.tar.bz2 coreboot-8bde652241ecb8356540b3a418012d3c7e570ac3.zip | |
drivers/intel/gma/opregion: Use CBFS cache to load VBT
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function
to load the VBT binary regardless of if it is compressed or not.
Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 251695eb4ed5..eea27fcb6c79 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -350,10 +350,6 @@ config CONSOLE_UART_BASE_ADDRESS default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE -config VBT_DATA_SIZE_KB - int - default 9 - # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) # ADL UART source clock: 100MHz |