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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-08-31 17:09:28 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-10-20 14:24:57 +0000 |
| commit | 0b0113f2436b448cd172d2ae9cfcc07628020173 (patch) | |
| tree | 627b1a81d647e9084763dd18eaca22022bd4568c /src/soc/intel/alderlake/chip.c | |
| parent | ce84a347bfa16f393e75e4cc63eded636ca69af8 (diff) | |
| download | coreboot-0b0113f2436b448cd172d2ae9cfcc07628020173.tar.gz coreboot-0b0113f2436b448cd172d2ae9cfcc07628020173.tar.bz2 coreboot-0b0113f2436b448cd172d2ae9cfcc07628020173.zip | |
device/device.h: Rename pci_domain_scan_bus
On all targets the domain works as a host bridge. Xeon-sp code intends
to feature multiple host bridges below a domain, hence rename the
function to pci_host_bridge_scan_bus.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.c')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 8b32b965b52a..063915798dcc 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -248,7 +248,7 @@ static void cpu_set_north_irqs(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, + .scan_bus = &pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, .acpi_fill_ssdt = ssdt_set_above_4g_pci, |