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| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2022-01-16 23:16:24 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-21 15:17:26 +0000 |
| commit | a6d642fa8da4c723a41ad96b317edd9d8e193460 (patch) | |
| tree | 4a86b3fda696062a7c824a648e8ec47edf48cb9d /src/soc/intel/alderlake/include | |
| parent | d2ca5be61a9bcf3e246546aa9eaaf87361a0a4ed (diff) | |
| download | coreboot-a6d642fa8da4c723a41ad96b317edd9d8e193460.tar.gz coreboot-a6d642fa8da4c723a41ad96b317edd9d8e193460.tar.bz2 coreboot-a6d642fa8da4c723a41ad96b317edd9d8e193460.zip | |
soc/intel/alderlake: Enable eMMC based on dev enabled
1. Add eMMC device function in pci_devs.h.
2. Enable eMMC device and configuration based on dev enabled.
3. Add SOC acpi name for eMMC.
Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 956a021b681c..b7196df0c300 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -166,6 +166,12 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PCH_DEV_SLOT_EMMC 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) +#define PCH_DEV_EMMC _PCH_DEV(EMMC, 0) +#endif + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) |