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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-02 16:16:48 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-12-06 12:31:09 +0000 |
| commit | 461ff1d3e653bee655e1afe32c1dc5ada80fab6c (patch) | |
| tree | 4b886156d6c9e0c695fb07ab2f80b41afc165801 /src/soc/intel/alderlake/romstage | |
| parent | 1883106c73bb0e36febd9a6be146665517fa755d (diff) | |
| download | coreboot-461ff1d3e653bee655e1afe32c1dc5ada80fab6c.tar.gz coreboot-461ff1d3e653bee655e1afe32c1dc5ada80fab6c.tar.bz2 coreboot-461ff1d3e653bee655e1afe32c1dc5ada80fab6c.zip | |
soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h
This enum is useful to have around for more than just the one file, so
move it to a common header file, and while we're there, also add an
option for UNKNOWN.
TEST=boot test on brya0
Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/romstage')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2d631413b2af..8959bf7d4662 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -23,11 +23,6 @@ #define CPU_PCIE_BASE 0x40 -enum pcie_rp_type { - PCH_PCIE_RP, - CPU_PCIE_RP, -}; - enum vtd_base_index_type { VTD_GFX, VTD_IPU, @@ -40,11 +35,11 @@ enum vtd_base_index_type { static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) { - assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP); + assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU); - if (type == PCH_PCIE_RP) + if (type == PCIE_RP_PCH) return rp_number; - else // type == CPU_PCIE_RP + else // type == PCIE_RP_CPU return CPU_PCIE_BASE + rp_number; } @@ -82,12 +77,12 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, /* Configure PCH PCIE ports */ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp, CONFIG_MAX_PCH_ROOT_PORTS); /* Configure CPU PCIE ports */ m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, + pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp, CONFIG_MAX_CPU_ROOT_PORTS); } |