diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-03-10 21:09:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:08:02 +0000 |
| commit | 77298c6820a0f4424a41d9f740f379f88f51e406 (patch) | |
| tree | 8b98460562808c3e205583f435b71af744bf618d /src/soc/intel/alderlake/systemagent.c | |
| parent | 8bd525001fa7d051965ffd2bad2e7e5ecd0dd547 (diff) | |
| download | coreboot-77298c6820a0f4424a41d9f740f379f88f51e406.tar.gz coreboot-77298c6820a0f4424a41d9f740f379f88f51e406.tar.bz2 coreboot-77298c6820a0f4424a41d9f740f379f88f51e406.zip | |
soc/intel/alderlake: add processor power limits control support
Add processor power limits control support to configure values for
alderlake soc based platforms.
BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board
Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/systemagent.c')
| -rw-r--r-- | src/soc/intel/alderlake/systemagent.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 35043c61ac40..eb1defc87aca 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -8,8 +8,11 @@ #include <device/device.h> #include <device/pci.h> +#include <delay.h> +#include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h> /* @@ -48,12 +51,20 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); - /* TODO: Add set_power_limits() */ + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |