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| author | Sean Rhodes <sean@starlabs.systems> | 2023-08-09 13:07:35 +0100 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-17 16:45:48 +0000 |
| commit | 2d482386182e4effa109fee6aa5acdf422557507 (patch) | |
| tree | 78895d9d4c4c7e9c5134de805d34dadbbddf01c9 /src/soc/intel/alderlake | |
| parent | c51e1682d575287a7b2844e94687cff4fdc4a2e7 (diff) | |
| download | coreboot-2d482386182e4effa109fee6aa5acdf422557507.tar.gz coreboot-2d482386182e4effa109fee6aa5acdf422557507.tar.bz2 coreboot-2d482386182e4effa109fee6aa5acdf422557507.zip | |
soc/intel/alderlake: Set PchHdaSdiEnable for Alder Lake
This UPD does exist for Alder Lake, so set it there also.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 59cd8ff1b83e..4fc409973444 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -250,9 +250,7 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); -#if CONFIG(SOC_INTEL_RAPTORLAKE) memcpy(m_cfg->PchHdaSdiEnable, config->pch_hda_sdi_enable, sizeof(m_cfg->PchHdaSdiEnable)); -#endif } static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |