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authorVarshit B Pandya <varshit.b.pandya@intel.com>2021-07-14 11:08:23 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-07-20 13:35:10 +0000
commit339f0e7e14c00d7e322fbfc3d0b69af9285bc963 (patch)
treefa6311c3b38626dbb3ddd3c255c54419ee9702c7 /src/soc/intel/alderlake
parentaefcab7ff60087d13b6300393faaad24b0403893 (diff)
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soc/intel/alderlake: Add support for I2C6 and I2C7
As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r--src/soc/intel/alderlake/Kconfig2
-rw-r--r--src/soc/intel/alderlake/acpi/serialio.asl12
-rw-r--r--src/soc/intel/alderlake/chip.c2
-rw-r--r--src/soc/intel/alderlake/chipset.cb2
-rw-r--r--src/soc/intel/alderlake/i2c.c8
-rw-r--r--src/soc/intel/alderlake/include/soc/serialio.h2
6 files changed, 27 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 677e14155f9b..743be57d8966 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -223,7 +223,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
config SOC_INTEL_I2C_DEV_MAX
int
- default 6
+ default 8
config SOC_INTEL_UART_DEV_MAX
int
diff --git a/src/soc/intel/alderlake/acpi/serialio.asl b/src/soc/intel/alderlake/acpi/serialio.asl
index f7bf45205844..a32595381841 100644
--- a/src/soc/intel/alderlake/acpi/serialio.asl
+++ b/src/soc/intel/alderlake/acpi/serialio.asl
@@ -38,6 +38,18 @@ Device (I2C5)
Name (_DDN, "Serial IO I2C Controller 5")
}
+Device (I2C6)
+{
+ Name (_ADR, 0x00100000)
+ Name (_DDN, "Serial IO I2C Controller 6")
+}
+
+Device (I2C7)
+{
+ Name (_ADR, 0x00100001)
+ Name (_DDN, "Serial IO I2C Controller 7")
+}
+
Device (SPI0)
{
Name (_ADR, 0x001e0002)
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 88b31954e60b..4a060af66280 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -78,6 +78,8 @@ const char *soc_acpi_name(const struct device *dev)
case PCH_DEVFN_I2C3: return "I2C3";
case PCH_DEVFN_I2C4: return "I2C4";
case PCH_DEVFN_I2C5: return "I2C5";
+ case PCH_DEVFN_I2C6: return "I2C6";
+ case PCH_DEVFN_I2C7: return "I2C7";
case PCH_DEVFN_SATA: return "SATA";
case PCH_DEVFN_PCIE1: return "RP01";
case PCH_DEVFN_PCIE2: return "RP02";
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index b05a1e9bb540..532ec3839545 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -79,6 +79,8 @@ chip soc/intel/alderlake
device pci 0d.2 alias tcss_dma0 off end
device pci 0d.3 alias tcss_dma1 off end
device pci 0e.0 alias vmd off end
+ device pci 10.0 alias i2c6 off end
+ device pci 10.1 alias i2c7 off end
device pci 10.6 alias thc0 off end
device pci 10.7 alias thc1 off end
device pci 12.0 alias ish off end
diff --git a/src/soc/intel/alderlake/i2c.c b/src/soc/intel/alderlake/i2c.c
index ef34e2ef1c68..5fcca2a9e766 100644
--- a/src/soc/intel/alderlake/i2c.c
+++ b/src/soc/intel/alderlake/i2c.c
@@ -25,6 +25,10 @@ int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
return 4;
case PCH_DEVFN_I2C5:
return 5;
+ case PCH_DEVFN_I2C6:
+ return 6;
+ case PCH_DEVFN_I2C7:
+ return 7;
}
return -1;
}
@@ -44,6 +48,10 @@ int dw_i2c_soc_bus_to_devfn(unsigned int bus)
return PCH_DEVFN_I2C4;
case 5:
return PCH_DEVFN_I2C5;
+ case 6:
+ return PCH_DEVFN_I2C6;
+ case 7:
+ return PCH_DEVFN_I2C7;
}
return -1;
}
diff --git a/src/soc/intel/alderlake/include/soc/serialio.h b/src/soc/intel/alderlake/include/soc/serialio.h
index e42af5f781ee..d1a9a015fe69 100644
--- a/src/soc/intel/alderlake/include/soc/serialio.h
+++ b/src/soc/intel/alderlake/include/soc/serialio.h
@@ -18,6 +18,8 @@ enum {
PchSerialIoIndexI2C3,
PchSerialIoIndexI2C4,
PchSerialIoIndexI2C5,
+ PchSerialIoIndexI2C6,
+ PchSerialIoIndexI2C7,
};
enum {