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| author | Usha P <usha.p@intel.com> | 2022-01-17 19:04:32 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-01 10:13:20 +0000 |
| commit | 4b4aa0bed6ac261e89e4598b6108097d1e1021c6 (patch) | |
| tree | 30901d0b9e03c76a72a67e627002dea80e334928 /src/soc/intel/alderlake | |
| parent | 01e426d217d20526b366ae431219d5a6d7f298e1 (diff) | |
| download | coreboot-4b4aa0bed6ac261e89e4598b6108097d1e1021c6.tar.gz coreboot-4b4aa0bed6ac261e89e4598b6108097d1e1021c6.tar.bz2 coreboot-4b4aa0bed6ac261e89e4598b6108097d1e1021c6.zip | |
soc/intel/alderlake: Add PMC register base for ADL-N
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated
from the FSP code.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/pch.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 69058347341e..60f3a851b70f 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -25,7 +25,12 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1080 +#else #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 +#endif + #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 |