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| author | Felix Singer <felixsinger@posteo.net> | 2023-06-03 06:12:57 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-08-20 02:19:36 +0000 |
| commit | 52fb64be42f3bade7d8a7b1bddc6e980fc209430 (patch) | |
| tree | 8c2a0916f0ff0f55748665fac701c4b19e287587 /src/soc/intel/alderlake | |
| parent | b61ee16fb3a6d7dd0acc788b36cae66709360bdf (diff) | |
| download | coreboot-52fb64be42f3bade7d8a7b1bddc6e980fc209430.tar.gz coreboot-52fb64be42f3bade7d8a7b1bddc6e980fc209430.tar.bz2 coreboot-52fb64be42f3bade7d8a7b1bddc6e980fc209430.zip | |
soc/intel/alderlake_n: Allow using the microcode repo
Allow users of Alderlake N processors to use the microcode repository
and also add their related microcode blob to the list of microcodes
which should be included in the coreboot rom.
Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 4 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5facb85339a9..406e03c24ce5 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -111,7 +111,6 @@ config SOC_INTEL_ALDERLAKE_PCH_M config SOC_INTEL_ALDERLAKE_PCH_N bool select SOC_INTEL_ALDERLAKE - select MICROCODE_BLOB_UNDISCLOSED help Choose this option if your mainboard has a PCH-N chipset. diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index bc3fe20bfe79..c36c7172d5bf 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -78,8 +78,9 @@ cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 # RPL-S/HX B0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 # 06-b7-00, 06-b7-02, 06-b7-05 RPL-S/HX A0, C0 and H0 missing +else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00 else -ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) # 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples # Missing 06-9a-02 ADL-P K0 # ADL-P L0, ADL-P R0 and ADL-M R0 @@ -87,7 +88,6 @@ cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04 # RPL-P/H J0, RPL-U Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-ba-02 endif -endif ifeq ($(CONFIG_STITCH_ME_BIN),y) |