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author | V Sowmya <v.sowmya@intel.com> | 2021-07-15 08:11:08 +0530 |
---|---|---|
committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-08-12 19:32:34 +0000 |
commit | c6d7166942728fd79ccea09a30faddf137916dc3 (patch) | |
tree | eca2daa6133954a9679826868f5c1bbc4e7f34d9 /src/soc/intel/alderlake | |
parent | 458708fc30c8ba606d2b3126a3ac15fe68be01b0 (diff) | |
download | coreboot-c6d7166942728fd79ccea09a30faddf137916dc3.tar.gz coreboot-c6d7166942728fd79ccea09a30faddf137916dc3.tar.bz2 coreboot-c6d7166942728fd79ccea09a30faddf137916dc3.zip |
soc/intel/alderlake: Configure the SKU specific parameters for VR domains
This patch configures the SKU specific power delivery parameters for the
VR domains.
+--------------+-------+-------+-------+-------+-----------+--------+
| SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time|
| | |(mOhms)|(mOhms)| (A) | (A) | (msec)|
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 |
+ +-------+-------+-------+-------+-----------+--------+
| | GT | 3.2 | 3.2 | 50 | 57 | 28000 |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 |
+ +-------+-------+-------+-------+-----------+--------+
| | GT | 3.2 | 3.2 | 50 | 40 | 28000 |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 |
+ +-------+-------+-------+-------+-----------+--------+
| | GT | 3.2 | 3.2 | 40 | 20 | 28000 |
+--------------+-------+-------+-------+-------+-----------+--------+
These config values are generated iPDG application with ADL-P platform
package tool and supports 15W/28W/45W SKU's.
RDC Kit ID for the iPDG tools,
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.
BUG=b:195033556
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/intel/alderlake/chip.h | 6 | ||||
-rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 4 | ||||
-rw-r--r-- | src/soc/intel/alderlake/include/soc/vr_config.h | 71 | ||||
-rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 116 |
5 files changed, 198 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index bb57560293ae..783a4453af16 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += vr_config.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 077a58df794f..248eedfd98af 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -15,6 +15,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> +#include <soc/vr_config.h> #include <stdint.h> /* Types of different SKUs */ @@ -391,6 +392,11 @@ struct soc_intel_alderlake_config { /* External Icc Max for VnnSx rail in mA */ int vnn_icc_max_ma; } ext_fivr_settings; + + /* VrConfig Settings. + * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT. + */ + struct vr_config domain_vr_config[NUM_VR_DOMAINS]; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 3d08573d2c6c..cb4552d3fee2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -615,6 +615,10 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS; + + /* VrConfig Settings for IA and GT domains */ + for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h new file mode 100644 index 000000000000..3bf3c4adca3b --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/vr_config.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* VR Settings for each domain */ + +#ifndef _SOC_VR_CONFIG_H_ +#define _SOC_VR_CONFIG_H_ + +#include <fsp/api.h> + +struct vr_config { + + /* The below settings will take effect when this is set to 1 for that domain. */ + bool vr_config_enable; + + /* AC and DC Loadline. + They are in 1/100 mOhms (ie. 1250 = 12.50 mOhms) and range is 0-6249. */ + uint16_t ac_loadline; + uint16_t dc_loadline; + + /* VR Icc Max limit. + Range is from 0-255A in 1/4 A units (400 = 100A). */ + uint16_t icc_max; + + /* Thermal Design Current time window. + Defined in milli seconds and range 1ms to 448s. */ + uint32_t tdc_timewindow; + + /* Thermal Design Current current limit. + Defined in 1/8A units and range is 0-4095. 1000 = 125A. */ + uint16_t tdc_currentlimit; +}; + +#define VR_CFG_AMP(i) (uint16_t)((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) +#define VR_CFG_TDC_AMP(i) (uint16_t)((i) * 8) + +/* VrConfig Settings for 4 domains + * 0 = IA core, 1 = GT + */ +enum vr_domain { + VR_DOMAIN_IA, + VR_DOMAIN_GT, + NUM_VR_DOMAINS +}; + +#define VR_CFG_ALL_DOMAINS_LOADLINE(ia, gt) \ + { \ + [VR_DOMAIN_IA] = VR_CFG_MOHMS(ia), \ + [VR_DOMAIN_GT] = VR_CFG_MOHMS(gt), \ + } + +#define VR_CFG_ALL_DOMAINS_ICC(ia, gt) \ + { \ + [VR_DOMAIN_IA] = VR_CFG_AMP(ia), \ + [VR_DOMAIN_GT] = VR_CFG_AMP(gt), \ + } + +#define VR_CFG_ALL_DOMAINS_TDC(ia, gt) \ + { \ + [VR_DOMAIN_IA] = ia, \ + [VR_DOMAIN_GT] = gt, \ + } + +#define VR_CFG_ALL_DOMAINS_TDC_CURRENT(ia, gt) \ + { \ + [VR_DOMAIN_IA] = VR_CFG_TDC_AMP(ia), \ + [VR_DOMAIN_GT] = VR_CFG_TDC_AMP(gt), \ + } + +void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *cfg); +#endif diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c new file mode 100644 index 000000000000..88a0c31225e5 --- /dev/null +++ b/src/soc/intel/alderlake/vr_config.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <fsp/api.h> +#include <soc/ramstage.h> +#include <soc/vr_config.h> +#include <console/console.h> +#include <intelblocks/cpulib.h> + +/* + * VR Configurations for IA and GT domains for ADL-P SKU's. + * + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | + * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + */ + +struct vr_lookup { + uint16_t mchid; + uint32_t conf[NUM_VR_DOMAINS]; +}; + +static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain, + const uint16_t mch_id) +{ + for (size_t i = 0; i < tbl_entries; i++) { + if (tbl[i].mchid != mch_id) + continue; + return tbl[i].conf[domain]; + } + + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); + return 0; +} + +static const struct vr_lookup vr_config_ll[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, +}; + +static const struct vr_lookup vr_config_icc[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(109, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, +}; + +static const struct vr_lookup vr_config_tdc_timewindow[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, +}; + +static const struct vr_lookup vr_config_tdc_currentlimit[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, +}; + +void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, + int domain, const struct vr_config *chip_cfg) +{ + const struct vr_config *cfg; + + if (domain < 0 || domain >= NUM_VR_DOMAINS) + return; + + /* Use device tree override if requested */ + if (chip_cfg->vr_config_enable) { + cfg = chip_cfg; + + s_cfg->AcLoadline[domain] = cfg->ac_loadline; + s_cfg->DcLoadline[domain] = cfg->dc_loadline; + s_cfg->IccMax[domain] = cfg->icc_max; + s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; + s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; + if (cfg->tdc_timewindow != 0 && cfg->tdc_currentlimit != 0) + s_cfg->TdcEnable[domain] = 1; + } else { + uint16_t mch_id = 0; + + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), + domain, mch_id); + s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), + domain, mch_id); + s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), + domain, mch_id); + s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow, + ARRAY_SIZE(vr_config_tdc_timewindow), + domain, mch_id); + s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, + ARRAY_SIZE(vr_config_tdc_currentlimit), + domain, mch_id); + if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) + s_cfg->TdcEnable[domain] = 1; + } +} |