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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 12:39:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-01 12:14:02 +0000 |
| commit | c7cfe0ba54bd280b8c4a5079bb2f6e19334f6dea (patch) | |
| tree | a7a769621549d3de3e8dd371544c74baee07bd38 /src/soc/intel/alderlake | |
| parent | 3657187789ee72834539b82cac6dda525421e4ed (diff) | |
| download | coreboot-c7cfe0ba54bd280b8c4a5079bb2f6e19334f6dea.tar.gz coreboot-c7cfe0ba54bd280b8c4a5079bb2f6e19334f6dea.tar.bz2 coreboot-c7cfe0ba54bd280b8c4a5079bb2f6e19334f6dea.zip | |
soc/intel: Refactor `xdci_can_enable()` function
The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.
Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index c814d8c3ee3b..7fe996e1f751 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -371,10 +371,7 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { - /* Enable xDCI controller if enabled in devicetree and allowed */ - if (!xdci_can_enable()) - devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); - s_cfg->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); + s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); } static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |