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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-10-28 15:53:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-20 14:06:42 +0000 |
| commit | ce14b611d4d24c8c89c3f4c685998237b62a695e (patch) | |
| tree | ec33556e067195a83729b1c34491806a0b0d7889 /src/soc/intel/alderlake | |
| parent | 1728e1bc15d124f6d080d867a40d2428327c831e (diff) | |
| download | coreboot-ce14b611d4d24c8c89c3f4c685998237b62a695e.tar.gz coreboot-ce14b611d4d24c8c89c3f4c685998237b62a695e.tar.bz2 coreboot-ce14b611d4d24c8c89c3f4c685998237b62a695e.zip | |
soc/intel/alderlake: Hook up the OC watchdog
Hook up the OC watchdog common block and initialize it if requested.
TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1ec207646bf4..2bfb07c9a1b4 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -65,6 +65,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 select SOC_INTEL_COMMON_BLOCK_MEMINIT + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index dfe3b323aa0a..a674b0acc65d 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -9,6 +9,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/cse.h> #include <intelblocks/early_graphics.h> +#include <intelblocks/oc_wdt.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/smbus.h> @@ -166,6 +167,8 @@ void mainboard_romstage_entry(void) struct chipset_power_state *ps = pmc_get_power_state(); bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; + setup_oc_wdt(); + /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); |