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| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-19 11:20:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-20 12:37:21 +0000 |
| commit | e71ea1e1b6a7769ae74f9933f5ae0321d85b2e3d (patch) | |
| tree | 6e036103fedc7f5645b9b48103068541e4c61a32 /src/soc/intel/apollolake/cse.c | |
| parent | 759bb4c00d818011c754e62afbe554b6a4cb52d4 (diff) | |
| download | coreboot-e71ea1e1b6a7769ae74f9933f5ae0321d85b2e3d.tar.gz coreboot-e71ea1e1b6a7769ae74f9933f5ae0321d85b2e3d.tar.bz2 coreboot-e71ea1e1b6a7769ae74f9933f5ae0321d85b2e3d.zip | |
soc/apollolake: Add CSE Firmware Status Registers
Add the CSE, General Status and Miscellaneous registers and
print information from them accordingly. All values were taken
from Intel document number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: Working State : 2
[DEBUG] CSE: Manufacturing Mode : NO
[DEBUG] CSE: Operation State : 1
[DEBUG] CSE: FW Init Complete : NO
[DEBUG] CSE: Error Code : 3
[DEBUG] CSE: Operation Mode : 0
[DEBUG] CSE: FPF status : unknown
Please note, the values shown are in an error state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1a5548132dadbb188a33a7ae30a0a1fa144d130f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake/cse.c')
| -rw-r--r-- | src/soc/intel/apollolake/cse.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 0f11809297cf..8473d20aefe5 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -8,6 +8,7 @@ #include <intelblocks/cse.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <soc/cse.h> #include <soc/heci.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> @@ -156,25 +157,32 @@ static uint32_t dump_status(int index, int reg_addr) static void dump_cse_state(void) { - uint32_t fwsts1; + union cse_fwsts1 fwsts1; if (!is_cse_enabled()) return; - fwsts1 = dump_status(1, PCI_ME_HFSTS1); + fwsts1.data = dump_status(1, PCI_ME_HFSTS1); dump_status(2, PCI_ME_HFSTS2); dump_status(3, PCI_ME_HFSTS3); dump_status(4, PCI_ME_HFSTS4); dump_status(5, PCI_ME_HFSTS5); dump_status(6, PCI_ME_HFSTS6); - /* Minimal decoding is done here in order to call out most important - pieces. Manufacturing mode needs to be locked down prior to shipping - the product so it's called out explicitly. */ - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - (fwsts1 & (1 << 0x4)) ? "YES" : "NO"); - - printk(BIOS_DEBUG, "ME: FPF status : "); + printk(BIOS_DEBUG, "CSE: Working State : %u\n", + fwsts1.fields.working_state); + printk(BIOS_DEBUG, "CSE: Manufacturing Mode : %s\n", + fwsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "CSE: Operation State : %u\n", + fwsts1.fields.operation_state); + printk(BIOS_DEBUG, "CSE: FW Init Complete : %s\n", + fwsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "CSE: Error Code : %u\n", + fwsts1.fields.error_code); + printk(BIOS_DEBUG, "CSE: Operation Mode : %u\n", + fwsts1.fields.operation_mode); + + printk(BIOS_DEBUG, "CSE: FPF status : "); switch (g_fuse_state) { case FUSE_FLASH_UNFUSED: printk(BIOS_DEBUG, "unfused"); |