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| author | Sean Rhodes <sean@starlabs.systems> | 2022-01-19 08:13:38 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 16:18:20 +0000 |
| commit | 2d58d5c0529d47e6639b250d65c7d2f5c7152650 (patch) | |
| tree | e3fdfc8f3ddac215d64ad47362a796ac94b3bac4 /src/soc/intel/apollolake | |
| parent | 7c2f57a4c7aee8ed63001d5db686917d17cf82f6 (diff) | |
| download | coreboot-2d58d5c0529d47e6639b250d65c7d2f5c7152650.tar.gz coreboot-2d58d5c0529d47e6639b250d65c7d2f5c7152650.tar.bz2 coreboot-2d58d5c0529d47e6639b250d65c7d2f5c7152650.zip | |
soc/apollolake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 21 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 4 |
2 files changed, 23 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index fe0cb9377a84..00c47f3d2896 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -17,6 +17,7 @@ #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/gpio.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -82,8 +83,24 @@ void bootblock_soc_early_init(void) /* Prepare UART for serial console. */ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); - if (CONFIG(DRIVERS_UART_8250IO)) - lpc_io_setup_comm_a_b(); + + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66; + + const config_t *config = config_of_soc(); + + + if (config->lpc_ioe) { + io_enables = config->lpc_ioe & 0x3f0f; + lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377); + } else { + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + } + + /* IO Decode Enable */ + lpc_enable_fixed_io_ranges(io_enables); if (CONFIG(TPM_ON_FAST_SPI)) tpm_enable(); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index f531381fac46..0073103e253b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -106,6 +106,10 @@ struct soc_intel_apollolake_config { uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ + /* LPC fixed enables and ranges */ + uint16_t lpc_iod; + uint16_t lpc_ioe; + /* Configure LPSS S0ix Enable */ uint8_t lpss_s0ix_enable; |