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authorSean Rhodes <sean@starlabs.systems>2022-07-28 21:55:35 +0100
committerSean Rhodes <sean@starlabs.systems>2022-12-22 21:16:13 +0000
commita49cd32da028d60e52d9e8078514c9a09a005710 (patch)
treea0ee0293c42ef0bae7286c71b76cbc25a419badd /src/soc/intel/apollolake
parent6a803bfae6e5a05becce68935957f25fb37181ff (diff)
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soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONF
The current implementation of the MCRS had several issues with BARs and MMCONF not being available: [ 0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb [ 0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window [ 0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit] ... [ 0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.138300] PCI: not using MMCONFIG [ 0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources [ 0.149679] PCI: not using MMCONFIG [ 0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge. This new MCRS, tested on the Star Lite Mk IV, resolves these issues: [ 0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb [ 0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit] ... [ 0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.138460] PCI: not using MMCONFIG [ 0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 22304336860d..b1ed3e56b4a2 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -122,5 +122,27 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
+Device (PDRC) /* PCI Device Resource Consumption */
+{
+ Name (_HID, EisaId("PNP0C02"))
+ Name (_UID, 1)
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ /* PCI Express BAR */
+ Memory32Fixed (ReadWrite,
+ CONFIG_ECAM_MMCONF_BASE_ADDRESS,
+ CONFIG_ECAM_MMCONF_LENGTH, PCIX)
+
+ /* Local APIC range (0xfee0_0000 to 0xfeef_ffff) */
+ Memory32Fixed (ReadOnly, 0x0fee00000, 0x00010000, LIOH)
+ })
+
+ Return (BUF0)
+ }
+}
+
/* GFX 00:02.0 */
#include <drivers/intel/gma/acpi/gfx.asl>