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| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-02-13 13:20:36 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:26:44 +0000 |
| commit | bb052ced54903e8543cba74649ff412fbcb8e1c5 (patch) | |
| tree | 16ac3823037646be5754852b1c0b2baa5f7eeffe /src/soc/intel/apollolake | |
| parent | 7c31d17317596c766ac15350560d76035cc8ef08 (diff) | |
| download | coreboot-bb052ced54903e8543cba74649ff412fbcb8e1c5.tar.gz coreboot-bb052ced54903e8543cba74649ff412fbcb8e1c5.tar.bz2 coreboot-bb052ced54903e8543cba74649ff412fbcb8e1c5.zip | |
soc/intel/apollolake: Fix overlapping ACPI resource ranges
The address space allotted to MCRS in the northbridge needs to be exclusive
of the address space allotted to the GPIO controllers in the southbridge,
otherwise Windows complains of overlapping resource ranges and disables
the GPIO controllers. To prevent overlap, use CONFIG_PCR_BASE_ADDRESS
to set the upper bound of MCRS rather than MMCONF.
Test: boot Windows 10/11 on google/{reef,ampton} and verify that
GPIO controllers are indicated as without fault in Device Manager.
Change-Id: I2117054edb448e717b7cbe80958c9c4e6c996e2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/northbridge.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 834e5e4170e7..b05dc5603ff1 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -79,8 +79,8 @@ Method (_CRS, 0, Serialized) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ PMIN = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 - /* Read MMCONF base */ - PMAX = \_SB.PCI0.MCHC.MCNF & 0xF0000000 + /* Use PCR base to ensure PMAX below GPIO controllers attached to _SB */ + PMAX = CONFIG_PCR_BASE_ADDRESS & 0xF0000000 /* Calculate PCI MMIO Length */ PLEN = PMAX - PMIN + 1 |