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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-18 19:40:48 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-19 19:31:08 +0000 |
| commit | 4f14cd8a39e65811af08296633842289efa42927 (patch) | |
| tree | 1cece9915f897af008d2d83701088b3054c4ab93 /src/soc/intel/baytrail/Kconfig | |
| parent | 6766f4fd046604e6376c9769cd5f8357dec6a80a (diff) | |
| download | coreboot-4f14cd8a39e65811af08296633842289efa42927.tar.gz coreboot-4f14cd8a39e65811af08296633842289efa42927.tar.bz2 coreboot-4f14cd8a39e65811af08296633842289efa42927.zip | |
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar
from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 94ed887d5c98..4e9223750eab 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -124,17 +124,6 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The baytrail romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n |