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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 17:25:38 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 10:17:40 +0000 |
| commit | e80d17f602e841e826e0892e4e44c9e1a9810cc0 (patch) | |
| tree | 43bde154b250343252fc6655492250b875681d93 /src/soc/intel/baytrail/bootblock/bootblock.c | |
| parent | e4109ff54ff3268fe65739e8efe79b57e67d2e3c (diff) | |
| download | coreboot-e80d17f602e841e826e0892e4e44c9e1a9810cc0.tar.gz coreboot-e80d17f602e841e826e0892e4e44c9e1a9810cc0.tar.bz2 coreboot-e80d17f602e841e826e0892e4e44c9e1a9810cc0.zip | |
soc/intel/baytrail: Retype some pointers
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/bootblock/bootblock.c')
| -rw-r--r-- | src/soc/intel/baytrail/bootblock/bootblock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 0f3980cefbde..62f42cd4d6e3 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -58,8 +58,8 @@ static void program_base_addresses(void) static void spi_init(void) { - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ |