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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-17 06:47:50 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-21 07:01:23 +0000 |
| commit | 8e23bac97ec66a49f9ddb1a4069e4e68666833fb (patch) | |
| tree | 92d982a32199bc827e59dc7d8da48a96e5d98599 /src/soc/intel/baytrail/include/soc/ramstage.h | |
| parent | 12b121cdb450d96309dd96b2ccc25fc5501d2250 (diff) | |
| download | coreboot-8e23bac97ec66a49f9ddb1a4069e4e68666833fb.tar.gz coreboot-8e23bac97ec66a49f9ddb1a4069e4e68666833fb.tar.bz2 coreboot-8e23bac97ec66a49f9ddb1a4069e4e68666833fb.zip | |
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/include/soc/ramstage.h')
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/ramstage.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index d20859d05501..f98a79b2ea66 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -23,7 +23,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); |