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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-03-16 19:02:26 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-14 19:45:56 +0000 |
| commit | 4bd9187dadaf4f3be5a1776d98d1f79cdfb23de8 (patch) | |
| tree | cadad49316ba0b6e77d9304a5505dcede8860ea5 /src/soc/intel/baytrail/ramstage.c | |
| parent | 3dc1792f1df9a9cd982bb63d3b29cc16c08bd7f6 (diff) | |
| download | coreboot-4bd9187dadaf4f3be5a1776d98d1f79cdfb23de8.tar.gz coreboot-4bd9187dadaf4f3be5a1776d98d1f79cdfb23de8.tar.bz2 coreboot-4bd9187dadaf4f3be5a1776d98d1f79cdfb23de8.zip | |
ACPI: Refactor use of global and device NVS
After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.
Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).
Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/ramstage.c')
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 0b681b021220..26e0b6e46d6b 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -13,6 +13,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> +#include <soc/device_nvs.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> @@ -116,6 +117,11 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } +size_t size_of_dnvs(void) +{ + return sizeof(struct device_nvs); +} + /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { |