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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-15 05:58:42 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:28:42 +0000 |
| commit | 4de1a31cb04f0363b6d257d9de392cdfe8d5644c (patch) | |
| tree | 80a674e5d82d33c5e133d31676ab48bad409798e /src/soc/intel/baytrail/ramstage.c | |
| parent | cdd2f63947549e9b478f26942daf400cf4f246e6 (diff) | |
| download | coreboot-4de1a31cb04f0363b6d257d9de392cdfe8d5644c.tar.gz coreboot-4de1a31cb04f0363b6d257d9de392cdfe8d5644c.tar.bz2 coreboot-4de1a31cb04f0363b6d257d9de392cdfe8d5644c.zip | |
ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/ramstage.c')
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index f1401e2411d5..28aa588c01a7 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -121,37 +121,38 @@ static void fill_in_pattrs(void) static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { uint16_t pm1; + int index; + pm1 = ps->pm1_sts & ps->pm1_en; /* Scan for first set bit in PM1 */ - for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + for (index = 0; index < 16; index++) { if (pm1 & 1) break; pm1 >>= 1; } - /* If unable to determine then return -1 */ - if (gnvs->pm1i >= 16) - gnvs->pm1i = -1; - - printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", - gnvs->pm1i); + if (index < 16) + gnvs->pm1i = index; } static void acpi_save_wake_source(void *unused) { const struct chipset_power_state *ps; - struct global_nvs *gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct global_nvs *gnvs; + if (acpi_reset_gnvs_for_wake(&gnvs) < 0) + return; if (acpi_pm_state_for_wake(&ps) < 0) return; pm_fill_gnvs(gnvs, ps); + + printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", + gnvs->pm1i); } -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, acpi_save_wake_source, NULL); static void baytrail_enable_2x_refresh_rate(void) { |