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| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-24 10:21:43 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-17 18:55:29 +0100 |
| commit | ae5d83ef84b1cd51e426d9e812ec40a7bc744e55 (patch) | |
| tree | fdfb239df9093d36ebde2a5f9bf8079a04c15542 /src/soc/intel/baytrail/ramstage.c | |
| parent | e18d68fbaccf9e0f9bafed7f7dc60dbe95d2f4fd (diff) | |
| download | coreboot-ae5d83ef84b1cd51e426d9e812ec40a7bc744e55.tar.gz coreboot-ae5d83ef84b1cd51e426d9e812ec40a7bc744e55.tar.bz2 coreboot-ae5d83ef84b1cd51e426d9e812ec40a7bc744e55.zip | |
baytrail: add support to run reference code blob
The reference code blob is needed to bootstrap
certain pieces of hardware in bay trail. Provide
the ability to run reference code by loading
the reference code as an rmodule.
Note that support for vboot verification and S3
resume is omitted from this commit.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with refcode loading.
Change-Id: I30334db441a57f4d87b4de6fca0a9a48e1c05c05
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174426
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4898
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/ramstage.c')
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 229e3679df91..896ecfe8d5fa 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -113,6 +113,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Run reference code. */ + baytrail_run_reference_code(); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); |