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| author | Kane Chen <kane.chen@intel.com> | 2015-01-17 08:19:54 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:18:19 +0200 |
| commit | ba9b7bfc6f4b6622fa2d272faeb32b7135287ee6 (patch) | |
| tree | 758efaa9b3d05a73c79481529872993e5904449e /src/soc/intel/baytrail/ramstage.c | |
| parent | ff0f460e764e24d4f7bae7e9dce8967f9cd3e36c (diff) | |
| download | coreboot-ba9b7bfc6f4b6622fa2d272faeb32b7135287ee6.tar.gz coreboot-ba9b7bfc6f4b6622fa2d272faeb32b7135287ee6.tar.bz2 coreboot-ba9b7bfc6f4b6622fa2d272faeb32b7135287ee6.zip | |
baytrail: add code for supporting 2x ddr refresh rate
this code change provides a way to enable 2x refresh rate
in RW image
In baytrail, it enables 2x refresh rate by default
BUG=chrome-os-partner:35210
BRANCH=none
TEST=check the register is set properly on rambi
Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: c740d403708862514be9fa24f56b2764328979eb
Original-Change-Id: I84f33d75ea7ebfea180b304e8ff683884f0dbe8a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241754
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9498
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/ramstage.c')
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 6c2de111dcbb..8b6d93cbe084 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -38,6 +38,7 @@ #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/ramstage.h> +#include <soc/iosf.h> /* Global PATTRS */ DEFINE_PATTRS; @@ -170,12 +171,24 @@ static void s3_resume_prepare(void) s3_save_acpi_wake_source(gnvs); } +static void baytrail_enable_2x_refresh_rate(void) +{ + u32 reg; + reg = iosf_dunit_read(0x8); + reg = reg & ~0x7000; + reg = reg | 0x2000; + iosf_dunit_write(0x8, reg); +} + void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) { struct soc_gpio_config *gpio_config; fill_in_pattrs(); + if (!config->disable_ddr_2x_refresh_rate) + baytrail_enable_2x_refresh_rate(); + /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); |