diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-15 12:51:51 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-29 17:34:12 +0000 |
| commit | 179da7fb5cff3c9034dc3203086c84342560c600 (patch) | |
| tree | a0ee100f05dd58d34f1412923227c86088edd696 /src/soc/intel/baytrail/romstage/pmc.c | |
| parent | 6229cc93ff16a5a9a424a0323fd631c8b3e1c943 (diff) | |
| download | coreboot-179da7fb5cff3c9034dc3203086c84342560c600.tar.gz coreboot-179da7fb5cff3c9034dc3203086c84342560c600.tar.bz2 coreboot-179da7fb5cff3c9034dc3203086c84342560c600.zip | |
soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCK
This moves programming BAR's and setting up console in the bootblock.
Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36873
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/pmc.c')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/pmc.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 2eb3846c4f5c..11b3b0f8bc19 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -14,7 +14,6 @@ */ #include <stddef.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> @@ -27,15 +26,6 @@ #include <soc/romstage.h> #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { |