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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-10-31 13:44:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-04 13:23:27 +0000 |
| commit | def74aacedd4f33829347037f12cfc213b46bc6c (patch) | |
| tree | 0046cc996ac4466c5109b5a6132e570deabdbae6 /src/soc/intel/baytrail | |
| parent | 059902882ce56502124375c9395ebe8b49640710 (diff) | |
| download | coreboot-def74aacedd4f33829347037f12cfc213b46bc6c.tar.gz coreboot-def74aacedd4f33829347037f12cfc213b46bc6c.tar.bz2 coreboot-def74aacedd4f33829347037f12cfc213b46bc6c.zip | |
soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.
Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 26de1cbc2077..4e8dc68e0805 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -1,19 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpi_pm.h> #include <bootstate.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> - #include <soc/device_nvs.h> #include <soc/gpio.h> +#include <soc/iosf.h> #include <soc/lpc.h> #include <soc/msr.h> #include <soc/nvs.h> @@ -21,7 +21,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/iosf.h> #define SHOW_PATTRS 1 |